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EL8176
Data Sheet October 26, 2006 FN7436.6
Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp
The EL8176 is a micropower precision operational amplifier optimized for single supply operation at 5V and can operate down to 2.4V. The EL8176 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. The EL8176 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails.
Features
* 55A supply current * 100V max offset voltage (8 Ld SO) * 2nA input bias current * 400kHz gain-bandwidth product * Single supply operation down to 2.4V * Rail-to-rail input and output * Output sources 31mA and sinks 26mA load current * Pb-free plus anneal available (RoHS compliant)
Applications
* Battery- or solar-powered systems * 4mA to 20mA current loops * Handheld consumer products * Medical devices * Thermocouple amplifiers * Photodiode pre amps * pH probe amplifiers
Ordering Information
PART PART NUMBER MARKING EL8176FWZ-T7 (Note) BBVA (Bottom) TAPE & REEL 7" (3k pcs) PACKAGE PKG. DWG. #
6 Ld SOT-23 MDP0038 (Pb-free)
EL8176FWZ-T7A BBVA (Note) (Bottom) EL8176FSZ (Note) EL8176FSZ-T7 (Note) 8176FSZ 8176FSZ
7" 6 Ld SOT-23 MDP0038 (250 pcs) (Pb-free) 7" (1k pcs) 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) MDP0027 MDP0027
Pinouts
EL8176 (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ 5 ENABLE 4 IN-
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
+-
EL8176 (8 LD SO) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 ENABLE 7 VS+ 6 VOUT 5 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8176
Absolute Maximum Ratings (TA = +25C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V, 1V/s Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and ENABLE . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VS+0.5V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS
VS = 5V, 0V, VCM = 0.1V, VO = 1.4V, VENH = 2.0V, VENL = 0.8V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. CONDITIONS 8 Ld SO MIN -100 -220 6 Ld SOT-23 -350 -350
80
DESCRIPTION Input Offset Voltage
TYP
25
MAX 100 220 350 350
UNIT V V V V V/Mo V/C
V OS -----------------Time V OS --------------T IOS
Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Offset Current -1 -4
2.4 0.7
0.4
1 4
nA nA nA nA VPP nV/Hz pA/Hz
IB
Input Bias Current
-2 -5
0.5
2 5
eN
Input Noise Voltage Peak-to-Peak Input Noise Voltage Density
f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz Guaranteed by CMRR test VCM = 0V to 5V 0 90 90 90 90
1 25 0.1 5 110
iN CMIR CMRR
Input Noise Current Density Input Voltage Range Common-Mode Rejection Ratio
V dB dB
PSRR
Power Supply Rejection Ratio VS = 2.4V to 5V
110
dB dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100k
200 200
500
V/mV V/mV
VO = 0.5V to 4.5V, RL = 1k VOUT Maximum Output Voltage Swing VOL; Output low, RL = 100k
25 3 8 10
V/mV mV mV mV mV V V
VOL; Output low, RL = 1k
130
200 300
VOH; Output high, RL = 100k
4.994 4.992
4.997
VOH; Output high, RL = 1k
4.750 4.7
4.867
V V
2
FN7436.6 October 26, 2006
EL8176
Electrical Specifications
PARAMETER SR GBW BW IS,ON VS = 5V, 0V, VCM = 0.1V, VO = 1.4V, VENH = 2.0V, VENL = 0.8V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) CONDITIONS MIN
0.065
DESCRIPTION Slew Rate Gain Bandwidth Product -3dB Bandwidth Supply Current, Enabled fO = 100kHz
TYP
0.13
MAX
0.3
UNIT V/s kHz MHz
400 1 35 30 55 75 90 3 10 10
Unity gain, CLOAD = 27pF, RF = 100
A A A A mA mA
IS,OFF
Supply Current, Disabled
IO+
Short Circuit Output Sourcing RL = 10 Current Short Circuit Output Sinking Current Minimum Supply Voltage RL = 10
18 18 17 15
31
IO-
26
mA mA
VS
Guaranteed by PSRR test
2.2
2.4 2.4
V V V V
VINH VINL IENH
Enable Pin High Level Enable Pin Low Level Enable Pin Input Current VEN = 5V 0.8 0.25 0.7
2
2.0 2.5
A A A A
IENL
Enable Pin Input Current
VEN = 0V
-0.5 -1
0
+0.5 +1
Typical Performance Curves
6 3 GAIN (dB) 0 -3 -6 -9 1k AV = 1 CL = 2.7pF RF = 100 RG = OPEN 10k VS = 2.5V VS = 1.0V VS = 1.25V 45 40 35 30 GAIN (dB) 25 20 15 10 5 100k FREQUENCY (Hz) 1M 10M AV = 100 RL = 10k CL = 2.7pF RF/RG = 99.02 RF = 221k RG = 2.23k 1k VS = 1.25V VS = 1.0V VS = 2.5V
0 100
10k FREQUENCY (Hz)
100k
1M
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
3
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
60 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V)
(Continued)
INPUT BIAS, OFFSET CURRENTS (pA)
10k
SUPPLY CURRENT (A)
1k
IB+
100
IOS
IB-
10
1 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT BIAS + OFFSET CURRENTS vs COMMON-MODE INPUT VOLTAGE
200 INPUT OFFSET VOLTAGE (V) INPUT OFFSET VOLTAGE (V) VCM = VDD/2 150 AV = -1 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 OUTPUT VOLTAGE (V) VDD = 2.5V VDD = 5V
0
-20
VOS, V
-40
-60
-80
-100 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V)
FIGURE 5. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
FIGURE 6. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
100 80 PHASE 60 GAIN (dB) 40
200 150
120
80
80 100 PHASE () 50 0 40 GAIN (dB)
40 PHASE ()
0
0
-40
20 0 -20 10
GAIN
-50 -40 -100 -150 1M -80 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) -120 10M -80
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 7. AVOL vs FREQUENCY @ 1k LOAD
FIGURE 8. AVOL vs FREQUENCY @ 100k LOAD
4
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
10.00 CURRENT NOISE (pA/Hz) VOLTAGE NOISE (nV/Hz)
(Continued)
1k
1.00
100
0.10
10
0.01 1 10 100 1k 10k 100k FREQUENCY (Hz)
1 10
100
1k FREQUENCY (Hz)
10k
100k
FIGURE 9. CURRENT NOISE vs FREQUENCY
FIGURE 10. VOLTAGE NOISE vs FREQUENCY
120 110 100 VOLTAGE NOISE (200nV/DIV) 90 CMRR (dB) 80 70 60 50 40 30 1VP-P 20 10 0 TIME (1s/DIV) 1 10 VCM = 0.2VPP 100 1k 10k 100k 1M VCM = 0.2VPP
FREQUENCY (Hz)
FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 12. CMRR vs FREQUENCY
120 110 100 90 PSRR (dB) 80 70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k 1M PSRRPSRR+ CURRENT (A)
75 n = 12 70 MEDIAN 65 60 55 50 45 -40 MIN MAX
-20
0
FREQUENCY (Hz)
20 40 60 80 TEMPERATURE (C)
100
120
FIGURE 13. PSRR vs FREQUENCY
FIGURE 14. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V ENABLED. RL = INF FIGURE 15.
5
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
7 6 CURRENT (A) 5 4 3 2 1 0 -40 MEDIAN MAX n = 12 CURRENT (nA)
(Continued)
2.5 n = 12 2 MAX 1.5 1 MEDIAN 0.5 0 MIN -0.5 -40
MIN
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 16. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V DISABLED. RL= INF
FIGURE 17. I BIAS (+) vs TEMPERATURE VS = 2.5V
3 n = 12 2.5 2 1.5 1 MEDIAN 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 MAX
2.5 n = 12 2 MAX CURRENT (nA) 1.5 1 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120
CURRENT (nA)
MEDIAN
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 18. I BIAS (+) vs TEMPERATURE VS = 1.2V
FIGURE 19. I BIAS (-) vs TEMPERATURE VS = 2.5V
3 2.5 CURRENT (nA) 2 1.5 1 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 MEDIAN n = 12
2.5 n = 12 2 CURRENT (nA) MAX 1.5 1 MEDIAN 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 20. I BIAS (-) vs TEMPERATURE VS = 1.2V
FIGURE 21. INPUT OFFSET CURRENT vs TEMPERATURE VS = 2.5V
6
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
2.5 n = 12 2 CURRENT (nA) 1.5 1 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 -50 -40 -20 MEDIAN MAX VOS (V) 100 150 MAX MEDIAN 50
(Continued)
200 n = 12
SO PACKAGE
0 MIN 0 20 40 60 80 100 120 TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 22. INPUT OFFSET CURRENT vs TEMPERATURE VS = 1.2V
FIGURE 23. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
200 n = 12 150 VOS (V) MAX MEDIAN
SO PACKAGE
400 300
n = 12 MAX
SOT-23 PACKAGE
200 VOS (V) 100 0
100
50
MEDIAN
0 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (C)
-100 -200 -40 MIN -20 0 20 40 60 80 100 120
-50 -40
TEMPERATURE (C)
FIGURE 24. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
FIGURE 25. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
200 150 100 VOS (V) 50 0 -50
n = 12
SOT-23 PACKAGE
125 n = 12 120
MAX CMRR (dB)
115 110
MAX
MEDIAN
MEDIAN 105 100 MIN
-100 -150 MIN -200 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C)
95 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
7
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
140 135 130 PSRR (dB) 125 VOUT (V) 120 115 110 105 100 95 -40 -20 MIN 0 20 40 60 80 100 120 MEDIAN MAX
(Continued)
n = 12
4.91 4.90 4.89 4.88 4.87 4.86 4.85 4.84 4.83 4.82 -40
n = 12 MAX MEDIAN
MIN
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 28. PSRR vs TEMPERATURE VS = 1.2V TO 2.5V
FIGURE 29. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
240 220 200 VOUT (mV)
n = 12
4.9982 4.9980 4.9978 4.9976 VOUT (V)
n = 12 MAX
180 160 MAX
4.9974 4.9972 4.9970 4.9968
MEDIAN
140 MEDIAN 120 100 80 -40 -20 MIN
MIN
4.9966 4.9964 20 40 60 80 100 120 4.9962 -40 -20 0 20 40 60 80 100 120
0
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 30. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
FIGURE 31. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
5.5 n = 12 5.0 SLEW RATE (V/s) 4.5 MAX 4.0 3.5 MEDIAN 3.0 2.5 -40 MIN -20 0 20 40 60 80 TEMPERATURE (C) 100 120
0.23 n = 12 0.21 0.19 0.17 MEDIAN 0.15 0.13 0.11 MIN 0.09 -40 -20 0 20 40 60 80 100 120 MAX
VOUT (mV)
TEMPERATURE (C)
FIGURE 32. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
FIGURE 33. +SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V, AV = 2
8
FN7436.6 October 26, 2006
EL8176 Typical Performance Curves
0.17 n = 12 0.16 CURRENT (pA) 0.15 AVOL (V/mV) 0.14 0.13 MIN 0.12 0.11 0.10 -40 MEDIAN MAX 900 800 700 600 500 400 300 200 100 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0 -40 -20 0 20 40 60 80 100 120 MAX MEDIAN MIN n = 12 SOT-23
(Continued)
TEMPERATURE (C)
FIGURE 34. -SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V, AV = 2
FIGURE 35. AVOL, RL = 100k VO @+2V/-2V @VS 2.5V
OUTPUT
OUTPUT
ENABLE INPUT
ENABLE INPUT
FIGURE 36. ENABLE DELAY TIME
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 909mW 0.8
J 8 /W S O 0 C 1 =1
A
FIGURE 37. DISABLE DELAY TIME
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1 POWER DISSIPATION (W)
0.7 POWER DISSIPATION (W)
0.6 625mW
J 8 /W SO 0 C 6 =1
0.5 0.4 391mW 0.3 0.2 0.1 0
A
0.6 435mW 0.4
0.2
SO T2 J 3-6 A =2 30 C /W
SO 25
JA =
T2 36 6 C/ W
0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
9
FN7436.6 October 26, 2006
EL8176 Applications Information
Introduction
The EL8176 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier as discussed below.
Input Bias Current Compensation
The input bias currents as low as 500pA are achieved while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL8176 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation is stable from -40C to +125C and operates from typically 10mV to the positive supply rail.
Rail-to-Rail Input
The input common-mode voltage range of the EL8176 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL8176 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL8176's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range for the EL8176 gives us an undistorted behavior from typically 10mV above the negative rail all the way up to the positive rail.
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL8176 with a 100k load will swing to within 3mV of the supply rails.
Enable/Disable Feature
The EL8176 offers an EN pin. The active low EN pin disables the device when pulled up to at least 2.0V. When disabled, the output is in a high impedance state and the part consumes typically 3A. When disabled, the high impedance output allows multiple parts to be MUXed together. When configured as a MUX, the outputs are tied together in parallel and a channel can be selected by pulling the EN pin to 0.8V or lower.The EN pin has an internal pull-down. If left open or floating, the EN pin will internally be pulled low, enabling the part by default.
10
FN7436.6 October 26, 2006
EL8176
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input impedance and low offset voltage of the EL8176, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 40 shows how the guard ring should be configured and Figure 41 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.
HIGH IMPEDANCE INPUT
IN 3 4 2 5 6 V+ EL8176 1
Typical Applications
R4 100k R3 R2 K TYPE THERMOCOUPLE 10k 10k V+ + EL8176 V-
410V/C + 5V
R1 100k
FIGURE 42. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The EL8176 is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The EL8176's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply.
FIGURE 40.
FIGURE 41.
11
FN7436.6 October 26, 2006
EL8176 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
12
FN7436.6 October 26, 2006
EL8176 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY SYMBOL A A1 A2 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. E 3/00 NOTES: 1. Plastic or metal protrusions of 0.25mm maximum per side are not included.
E1 2 3
E
b c D
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). 6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7436.6 October 26, 2006

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